1. Field of the Invention
The present invention relates to a flip-flop circuit that operates at high-speed at a low voltage, and, more particularly, to a high-speed flip-flop circuit that makes it possible to avoid instability in a low speed clock operation.
2. Description of the Related Art
An LSI chip contains a large number of flip-flop circuits. Known flip-flops that operate at high-speed include dynamic-type flip-flop circuits that capture data in response to the clock. Conventional dynamic type flip-flop circuits have a CMOS transfer gate provided on the input side of the inverters and between the inverters, capture input data and performs data transfers to a subsequent stage by turning a CMOS transfer gate on and off under the control of the clock. A dynamic-type flip-flop circuit of this kind is mentioned in Japanese Patent Application Laid Open No. H3-228296 (published on Oct. 9, 1991) and Japanese Patent Application Laid Open No. 2002-208841 (published on Jul. 26, 2002), for example.
In keeping with the higher speeds of LSIs in recent years, signal transfers between chips and signal transfers between circuit blocks and elements in a chip have become faster and faster. Accordingly, flip-flop circuits, which are provided in great numbers in an LSI chip, are now also required to operate at higher speeds. In this case, a dynamic-type flip-flop circuit that uses the CMOS transfer gate above is unsuitable for high-speed operations on account of the delay time caused by the transfer gates.
On the other hand, dynamic-type flip-flop circuits that do not use transfer gates have also been proposed (Japanese Patent Application Laid Open No. 2002-26697 (published on Jan. 25, 2002), for example). In this flip-flop circuit, a clock-controlled PMOS transistor and NMOS transistor are inserted in the CMOS inverter to capture input data in sync with clocks.
The dynamic-type flip-flop circuit above has a total of four transistors, which are two transistors for clock control and two transistors that constitute the CMOS inverter, connected between ground and the power supply. Hence, the power supply voltage cannot be lowered and therefore a dynamic-type flip-flop circuit of this kind is not suited to low power consumption.
On the other hand, a flip-flop circuit that is capable of operating in correspondence with a high-speed clock is also required to operate stably with respect to a low speed clock. That is, even in cases where the control clock frequencies extend over a broad frequency band, such a flip-flop circuit is required to operate without malfunctioning.